One type of non-volatile memory is resistive memory. Resistive memory utilizes the resistance value of a memory element to store one or more bits of data. For example, a memory element programmed or “set” to a low resistance value may represent a logic “0” data bit value, and a memory element programmed or “reset” to a high resistance value may represent a logic “1” data bit value. Typically, the resistance value of the memory element is electrically switched by applying a voltage pulse or a current pulse to the memory element.
One type of resistive memory is phase change memory. Phase change memory uses a phase change material in the resistive memory element. The phase change material exhibits at least two different states. The states of the phase change material may be referred to as an amorphous state and as a crystalline state, where the amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered lattice. The amorphous state usually exhibits higher resistivity than the crystalline state. Some phase change materials exhibit multiple crystalline states, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state, which have different resistivities and may be used to store bits of data. In the present disclosure, the amorphous state generally refers to the state having the higher resistivity while the crystalline state generally refers to the state having the lower resistivity.
Phase changes in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state and from the crystalline state to the amorphous state in response to temperature changes. The temperature changes of the phase change material may be achieved by driving current through the phase change material itself or by driving current through a resistive heater adjacent the phase change material. With both of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material.
A phase change memory including a memory array having a plurality of memory cells employing phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material. The temperature of the phase change material in each memory cell generally corresponds to the level of current and/or voltage applied to achieve the heating. The power used to program a memory cell is based on the electrical and thermal interface between the phase change material and at least one electrode contacting the phase change material.
For some non-volatile memories, such as FLASH memories, for example, potential memory errors are reduced by performing a read operation subsequent to a write operation (a so-called “verify read”) to identify/detect memory cells which are too close to the margins of a predetermined sensing window. Such memory cells are sometimes referred to as “weak cells” or “weak bits”. According to some techniques, error correction code techniques are applied to correct such weak bits, while other techniques perform a so-called “hard read” wherein a reference value is changed around a nominal read condition. With respect to FLASH memories, a verify read operation can be “hidden” since the timing is substantially the same as a normal read operation.
However, with respect to phase change memories, conventional techniques typically employ two additional read operations to verify that an acceptable write distribution (as measured by memory cell resistance levels) has been achieved. The two additional reads operation are commonly referred to as a “verify SET” and a “verify RESET” (and referred to collectively as a “two-sided read”), and respectively ensure that the resistance value of a phase change memory cell has an acceptable margin with respect to an expected SET resistance distribution and with respect to an expected RESET resistance distribution. While the duration of a verify SET does not exceed that of a standard READ operation of the phase change memory (e.g. 40 ns), a verify RESET, due to the large resistances of cells in the RESET state, has a much longer duration (e.g. 600 ns) which slows the operating speed of the phase change memory. This slow operating speed, relative to FLASH memories, generally prevents phase change memories from replacing FLASH memories in many applications.
For these and other reasons, there is a need for the present invention.